1. Field of the Invention:
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor device configuration in which memory cells are formed with high density.
2. Description of the Prior Art:
An exemplary arrangement of memory cells and sense amplifiers in a prior art dynamic random access memory (DRAM) is shown in FIG. 10. In this example, a DRAM of a folded bit line type is described. In a memory cell array 11, m word lines W.sub.j (j=0, 1, . . . , m-1), and n bit line pairs BL.sub.i, BL.sub.i (i=0, 1, . . . , n-1) which cross the word lines W.sub.j at right angles are formed. Memory cells 11a are formed at alternate crossings of the bit line pairs BL.sub.i, BL.sub.i and the word lines W.sub.j.
At the side of the memory cell array 11, a sense amplifier array 12 is formed. In the sense amplifier array 12, a plurality of sense amplifiers 12a are formed. Each of the plurality of sense amplifiers 12a is connected to a bit line pair BL.sub.i, BL.sub.i. The sense amplifier 12a is a circuit for differentially amplifying a small potential difference between a bit line BL.sub.i and a paired bit line BL.sub.i, so as to read out data stored in the memory cells 11a. Accordingly, it is necessary to provide the sense amplifier 12a for each bit line pair.
In FIG. 10, the reference label A indicates a region on the memory cell array 11 in which two columns of memory cells 11a to be connected to a common sense amplifier 12a are formed. Conventionally, the sense amplifier 12a is formed in a region having substantially the same width as that of the region A. The term "width" used herein means a length in a direction along the word lines W.sub.j, unless the measuring direction is mentioned.
FIG. 11 schematically shows the arrangement of the above-mentioned memory cell array 11, and sense amplifier array 12. In FIG. 11, the reference label MA denotes a region in which the memory cell array 11 is formed, and SAA denotes a region in which the sense amplifier array 12 is formed. The reference label STN denotes a shunt region formed between the memory cell arrays 11. The shunt region is a region for shunting by forming a metal interconnection layer on the interconnection layer of the word lines W.sub.j. The shunt region STN prevents a signal delay on the word lines W.sub.j.
A technique for preventing a signal delay on the word lines W.sub.j by providing the shunt region STN between the memory cell array forming regions MA, a so-called Al shunt technique, will be briefly described. Usually, the word lines are formed from an interconnection of a polycrystalline silicon film (polysilicon gate) or an interconnection of a polycrystalline silicon film and a silicide film formed thereon (polycide gate). The reason why the above-mentioned films are used as a material of the word lines is that, since these films have a higher melting point than that of an aluminum (Al) film, these films are suitable for a self-align gate process. However, these films have a disadvantage in that they have a higher specific resistance than that of the Al film. For this reason, an Al interconnection is provided on a layer of these films in which the word lines are formed, and the Al interconnection and the word lines are connected at a plurality of points. As a result, wiring resistance as a whole are reduced.
The shunt region STN is provided between the memory cell array forming regions MA for the above-described reasons. However, as a result, a dummy pattern of a memory cell or a pattern for reducing a difference in level between the shunt region STN and the memory cell array forming regions MA is required. Especially when a stacked memory cell is used, a wide pattern for reducing a difference in level is required. The reason is as follows. In the stacked memory cell, a capacitor is formed on a MOS transistor, so that the difference in level between the memory cell array forming region MA and the shunt region STN is large. As a result, it has been found that the shunt region STN occupies a relatively large area on a chip. Conventionally, a region at the side of the shunt region STN is not utilized.
As the DRAM is made to have a larger capacity in a given area, it is required to form memory cells 11a with higher density. This leads to the width of the region A on the memory cell array 11 needing to be made smaller. However, there is a limit to how much smaller the width of the sense amplifier 12a can be made. The reason is as follows. Since a transistor in the sense amplifier 12a is desired to be capable of detecting a very small potential difference, it is necessary to make the channel length and the width of source/drain regions larger than those of a usual transistor. If the channel of the transistor is short, there exists a possibility that the threshold voltage of the transistor will vary. If the source/drain regions are narrow, the imbalance of capacitance on the input terminal side of the sense amplifier 12a increases. Thus, in the DRAM having a larger capacity, there exists a problem in that it is difficult to maintain the sensitivity of the sense amplifier 12a.
As a countermeasure against the above problem, an arrangement has been proposed as is shown in FIG. 12 in which sense amplifier arrays 12 and 13 are located at both sides of the memory cell array 11. For example, see Japanese Laid-Open Patent Publication No. 2-181964. With this arrangement, bit line pairs are alternately connected to sense amplifiers 12a on the sense amplifier array 12 at one side and to sense amplifiers 13a on the sense amplifier array 13 at the other side. As a result, the width of each of the regions which are necessary for forming the sense amplifiers 12a and 13a can be made to be twice as large as that of the region A which is necessary for forming two columns of memory cells 11a.
However, when the sense amplifier arrays 12 and 13 are located at both the sides of the memory cell array 11, the area occupied by the sense amplifier arrays 12 and 13 is increased. This causes a problem in that the area of a chip becomes large.
Furthermore, when the capacity of the DRAM exceeds 64 megabits according to this arrangement, the width of the region A on the memory cell array 11 still must be made smaller. This causes a problem in that it is difficult to maintain the sensitivity of the sense amplifiers 12a and 13a for the same reasons mentioned above.
FIG. 13 schematically shows an arrangement of memory cell arrays 11 and column decoders 14. In FIG. 13, the reference label M indicates a region in which a memory cell column consisting, for example, of eight columns of memory cells corresponding to one column decoder 14 is formed. The column decoders 14 are located at the same intervals as those of the memory cell columns in the direction along the word lines. Accordingly, the width of the column decoder 14 is limited by the width of the memory cell forming region M. Therefore, in order to ensure the area of the column decoder 14, it is necessary to ensure the length of the column decoder 14 in a direction along the bit lines.